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Design software / FPGA - Resampler
RFELs flexible architecture supports up-sampling or down-sampling of many channels simultaneously and allows the rate change to be selected with a resolution of less than one Hertz. When operating on multiple input channels, the architecture treats each channel independently allowing different input/output sampling rates and rate changes for each. Furthermore, the rate change required for each channel can be updated at run-time, without affecting the operation of other channels.Silicon usage minimised for each application.
Supported by bit-true MATLAB models.
Xilinx and Altera FPGA devices supported.
Adjustable bit widths and bit growths (factory set).